View AM42BDS640AGBD8IT_2624763.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

!"

#

$
%

!" continuity of specifications

"

%
"
%
" continuity of ordering part numbers ! &
'(')("
%
*+,
" for more information + ! " am42bds640ag data sheet publication number 26445 revision b amendment 0 issue date november 1, 2002
preliminary t his document contains information on a product under development at advanced micro devices. the information i s intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed p roduct without notice. publication# 26445 rev: b amendment/ 0 issue date: november 1, 2002 refer to amd?s website (www.amd.com) for the latest information. am42bds640ag stacked multi-chip package (mcp) flash memory and sram am29bds640g 64 megabit (4 m x 16-bit) cmos 1.8 volt-only, simu ltaneous operation, burst mode flash memory and 16 mbit (1 m x 16-bit) static ram distinctive characteristics mcp features power supply voltage of 1.65 to 1.95 volt high performance ? access time as fast as 70 ns package ? 93-ball fbga operating temperature ? ?40c to +85c flash memory features architectural advantages single 1.8 volt read, program and erase (1.65 to 1.95 volt) manufactured on 0.17 m process technology simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in other bank ? zero latency between read and write operations ? four bank architecture: 16mb/16mb/16mb/16mb programmable burst interface ? 2 modes of burst read operation ? linear burst: 8, 16, and 32 words with wrap-around ? continuous sequential burst sector architecture ? eight 8 kword sectors and one hundred twenty-six 32 kword sectors ? banks a and d each contain four 8 kword sectors and thirty-one 32 kword sectors; banks b and c each contain thirty-two 32 kword sectors ? eight 8 kword boot sectors, four at the top of the address range, and four at the bottom of the address range minimum 1 million erase cycle guarantee per sector 20-year data retention at 125c performance charcteristics read access times at 54/40 mhz ? burst access times of 13.5/20 ns @ 30 pf at industrial temperature range ? asynchronous random access times of 70 ns (at 30 pf) ? synchronous latency of 87.5/95 ns power dissipation (typical values, c l = 30 pf) ? burst mode read: 10 ma ? simultaneous operation: 25 ma ? program/erase: 15 ma ? standby mode: 0.2 a hardware features software command sector locking handshaking: host monitors operations via rdy output hardware reset input (reset#) wp# input ? write protect (wp#) function protects sectors 0, 1 (bottom boot) or sectors 132 and 133 (top boot), regardless of sector protect status acc input: acceleration function reduces programming time; all sectors locked when acc = v il cmos compatible inputs, cmos compatible outputs low v cc write inhibit software features supports common flash memory interface (cfi) software command set compatible with jedec 42.4 standards data# polling and toggle bits erase suspend/resume ? suspends or resumes an erase operation in one sector to read data from, or program data to, other sectors unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences sram features power dissipation ? operating: 3 ma maximum ? standby: 15 a maximum ce1s# and ce2s chip select power down features using ce1s# and ce2s data retention supply voltage: 1.0 to 2.2 volt byte data control: lb#s (dq7?dq0), ub#s (dq15?dq8)
2 am42bds640ag november 1, 2002 preliminary general description the am29bds640g is a 64 mbit, 1.8 volt-only, simulta- neous read/write, burst mode flash memory device, orga- nized as 4,194,304 words of 16 bits each. this device uses a single v cc of 1.65 to 1.95 v to read, program, and erase the memory array. a 12.0-volt v id may be used for faster pro- gram performance if desired. the device can also be pro- grammed in standard eprom programmers. at 54 mhz, the device provides a burst access of 13.5 ns at 30 pf with a latency of 87.5 ns at 30 pf. at 40 mhz, the de- vice provides a burst access of 20 ns at 30 pf with a latency of 95 ns at 30 pf. the device operates within the industrial temperature range of -40c to +85c. the device is offered in a 93-ball fbga package. the simultaneous read/write architecture provides simul- taneous operation by dividing the memory space into four banks. the device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. this releases the system from wait- ing for the completion of program or erase operations. the device is divided as shown in the following table: the device uses chip enable (ce#), write enable (we#), address valid (avd#) and output enable (oe#) to control asynchronous read and write operations. for burst opera- tions, the device additionally requires ready (rdy), and clock (clk). this implementation allows easy interface with minimal glue logic to a wide range of microprocessors/micro- controllers for high performance read operations. the burst read mode feature gives system designers flexibil- ity in the interface to the device. the user can preset the burst length and wrap through the same memory space, or read the flash array in continuous mode. the clock polarity feature pr ovides system designers a choice of active clock edges, either rising or falling. the ac- tive clock edge initiates burst accesses and determines when data will be output. the device is entirely command set compatible with the jedec 42.4 single-power-supply flash standard . com- mands are written to the command register using standard microprocessor write timing. register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch ad- dresses and data needed for the programming and erase operations. reading data out of the device is similar to read- ing from other flash or eprom devices. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the system microprocessor to read boot-up firm- ware from the flash memory device. the host system can detect whether a program or erase op- eration is complete by using the device status bit dq7 (data# polling) and dq6/dq2 (toggle bits). after a program or erase cycle has been completed, the device automatically returns to reading array data. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc de- tector that automatically inhibits write operations during power transitions. the device also offers two types of data protection at the sector level. the sector lock/unlock com- mand sequence disables or re-enables both program and erase operations in any sector. when at v il , wp# locks sec- tors 0 and 1 (bottom boot device) or sectors 132 and 133 (top boot device). the device offers two power-saving features. when ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power con- sumption is greatly reduced in both modes. amd?s flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electri- cally erases all bits within a sector simultaneously via fowler-nordheim tunnelling. the data is programmed using hot electron injection. bank quantity size a 4 8 kwords 31 32 kwords b 32 32 kwords c 32 32 kwords d 31 32 kwords 4 8 kwords
november 1, 2002 am42bds640ag 3 preliminary table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 5 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 flash memory block diagram. . . . . . . . . . . . . . . . 6 flash memory simultaneous operation diagram 7 connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 8 special package handling instructions .................................... 8 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ordering information . . . . . . . . . . . . . . . . . . . . . . 10 mcp device bus operations. . . . . . . . . . . . . . . . 11 table 1. device bus operations ..................................................... 12 flash device bus operations . . . . . . . . . . . . . . . 13 requirements for asynchronous read operation (non-burst) ............................................................ 13 requirements for synchronous (burst) read operation ........ 13 8-, 16-, and 32-word linear burst with wrap around ......... 13 table 2. burst address groups .......................................................13 burst mode configuration register ........................................ 14 reduced wait-state handshaking option .............................. 14 simultaneous read/write operations with zero latency ....... 14 writing commands/command sequences ............................ 14 accelerated program operation .......................................... 14 autoselect functions ........................................................... 15 standby mode ........................................................................ 15 automatic sleep mode ........................................................... 15 reset#: hardware reset input ............................................. 15 output disable mode .............................................................. 15 hardware data protection ...................................................... 15 write protect (wp#) ............................................................. 16 low v cc write inhibit ........................................................... 16 write pulse ?glitch? protection ............................................ 16 logical inhibit ...................................................................... 16 power-up write inhibit ......................................................... 16 common flash memory interface (cfi) . . . . . . . 16 table 3. cfi query identification string ..........................................16 system interface string................................................................... 17 table 5. device geometry definition .............................................. 17 table 6. primary vendor-specific extended query ........................18 table 7. sector address table ........................................................19 flash command definitions . . . . . . . . . . . . . . . . 23 reading array data ................................................................ 23 set burst mode configuration register command sequence 23 figure 1. synchronous/asynchronous state diagram .................... 23 read mode setting .............................................................. 23 programmable wait state configuration ............................. 23 table 8. programmable wait state settings ...................................24 handshaking option ............................................................ 24 table 9. initial access codes ..........................................................24 standard handshaking operation ....................................... 24 table 10. wait states for standard handshaking ...........................24 burst read mode configuration .......................................... 24 table 11. burst read mode settings ..............................................25 burst active clock edge configuration ................................ 25 rdy configuration ............................................................... 25 configuration register ............................................................ 25 table 12. burst mode configuration register .................................25 sector lock/unlock command sequence .............................. 25 reset command ..................................................................... 25 autoselect command sequence ............................................ 26 table 13. device ids ...................................................................... 26 program command sequence ............................................... 26 unlock bypass command sequence .................................. 27 figure 2. erase operation.............................................................. 27 chip erase command sequence ........................................... 27 sector erase command sequence ........................................ 28 erase suspend/erase resume commands ........................... 28 figure 3. program operation ......................................................... 29 command definitions ............................................................. 30 table 14. command definitions .................................................... 30 flash write operation status . . . . . . . . . . . . . . . 31 dq7: data# polling ................................................................. 31 figure 4. data# polling algorithm .................................................. 31 rdy: ready ............................................................................ 32 dq6: toggle bit i .................................................................... 32 figure 5. toggle bit algorithm........................................................ 32 dq2: toggle bit ii ................................................................... 32 table 15. dq6 and dq2 indications .............................................. 33 reading toggle bits dq6/dq2 ............................................... 33 dq5: exceeded timing limits ................................................ 33 dq3: sector erase timer ....................................................... 34 table 16. write operation status ................................................... 34 absolute maximum ratings . . . . . . . . . . . . . . . . 35 figure 6. maximum negative overshoot waveform ...................... 35 figure 7. maximum positive overshoot waveform........................ 35 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 35 flash dc characteristics . . . . . . . . . . . . . . . . . . 36 sram dc and operating characteristics . . . . . 37 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 8. test setup....................................................................... 38 table 17. test specifications ......................................................... 38 key to switching waveforms. . . . . . . . . . . . . . . . 38 figure 9. input waveforms and measurement levels ................... 38 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39 sram ce#s timing ................................................................ 39 figure 10. timing diagram for alternating between sram and flash ............................................................. 39 synchronous/burst read ........................................................ 40 figure 11. clk synchronous burst mode read (rising active clk).......................................................................... 41 figure 12. clk synchronous burst mode read (falling active clock) ..................................................................... 42 figure 13. synchronous burst mode read .................................... 43 figure 14. 8-word linear burst with wrap around ......................... 43 figure 15. burst with rdy set one cycle before data ................. 44 figure 16. reduced wait-state handshaking burst mode read starting at an even address .......................................................... 45 figure 17. reduced wait-state handshaking burst mode read starting at an odd address............................................................ 46 asynchronous read ............................................................... 47 figure 18. asynchronous mode read with latched addresses .... 47 figure 19. asynchronous mode read............................................ 48 figure 20. reset timings ............................................................... 49 erase/program operations ..................................................... 50 figure 21. asynchronous program operation timings .................. 51 figure 22. alternate asynchronous program operation timings... 52 figure 23. synchronous program operation timings.................... 53
4 am42bds640ag november 1, 2002 preliminary figure 24. alternate synchronous program operation timings ..... 54 figure 25. chip/sector erase command sequence ....................... 55 figure 26. accelerated unlock bypass programming timing......... 56 figure 27. data# polling timings (during embedded algorithm) ... 57 figure 28. toggle bit timings (during embedded algorithm)......... 57 figure 29. synchronous data polling timings/toggle bit timings . 58 figure 30. latency with boundary crossing ................................... 59 figure 31. latency with boundary crossing into program/erase bank ................................................................ 60 figure 32. example of wait states insertion (standard handshaking device) ...................................................................... 61 figure 33. back-to-back read/write cycle timings ....................... 62 sram ac characteristics . . . . . . . . . . . . . . . . . . 63 read cycle ............................................................................. 63 figure 34. sram read cycle?address controlled....................... 63 figure 35. sram read cycle ......................................................... 64 write cycle ............................................................................. 65 figure 36. sram write cycle?we# control ................................ 65 figure 37. sram write cycle?ce1#s control ............................. 66 figure 38. sram write cycle?ub#s and lb#s control ............... 67 flash erase and programming performance . 68 flash latchup characteristics. . . . . . . . . . . . . . . 68 package pin capacitance . . . . . . . . . . . . . . . . . . 68 flash data retention . . . . . . . . . . . . . . . . . . . . . . 68 sram data retention . . . . . . . . . . . . . . . . . . . . . 69 figure 39. ce1#s controlled data retention mode....................... 69 figure 40. ce2s controlled data retention mode......................... 69 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 70 fsc093?93-ball fine-pitch grid array 8 x 11.6 mm ............ 70 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 71 revision a (may 20, 2002) ..................................................... 71
november 1, 2002 am42bds640ag 5 preliminary product selector guide mcp block diagram part number am42bds640ag burst frequency 54 mhz 40 mhz speed option v cc, v io = 1.65 ? 1.95 v d8, d9 c8, c9 flash max initial synchronous access time, ns (t iacc ) reduced wait-state handshaking: even address 87.5 95 max initial synchronous access time, ns (t iacc ) reduced wait-state handshaking: odd address; or standard handshaking 106 120 max burst access time, ns (t bacc )13.520 max asynchronous access time, ns (t acc ) 70 85 max ce# access, ns (t ce ) max oe# access, ns (t oe )13.520 sram max access time, ns (t acc ) 70 85 max ce# access, ns (t ce ) max oe# access, ns (t oe )3540 v ss v cc s reset# we# ce#f oe# ce1#s v ss v cc f/v io f rdy lb#s ub#s wp# ce2s 16 m bit static ram 64 m bit flash memory dq15 to dq0 dq15 to dq0 dq15 to dq 0 a 21 to a0 a0 to a19 acc avd# clk a19 to a0 a21 to a0
6 am42bds640ag november 1, 2002 preliminary flash memory block diagram input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v ssio v io we# reset# wp# acc ce# oe# dq15 ? dq0 data latch y-gating cell matrix address latch a21?a0 rdy buffer rdy burst state control burst address counter avd# clk
november 1, 2002 am42bds640ag 7 preliminary flash memory simultaneous operation diagram v ss v cc v io v ssio bank b address reset# acc we# ce# avd# rdy dq15?dq0 wp# state control & command register bank b x-decoder y-decoder latches and control logic bank a x-decoder y-decoder latches and control logic dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 bank c y-decoder x-decoder latches and control logic bank d y-decoder x-decoder latches and control logic oe# status control a21?a0 a21?a0 a21?a0 a21?a0 a21?a0 bank c address bank d address bank a address
8 am42bds640ag november 1, 2002 preliminary connection diagram note: v io f must be tied to v cc f. special package handling instructions special handling is required for flash memory prod- ucts in molded packages (tsop, bga, plcc, pdip, ssop). the package and/or data integrity may be compromised if the pack age body is exposed to tem- peratures above 150 c for prolonged periods of time. nc f1 g1 e2 f2 g2 h2 j2 l2 d3 e3 f3 g3 h3 j3 l3 d4 e4 f4 g4 h4 j4 l4 b5 d5 e5 h5 j5 l5 b6 d6 e6 h6 j6 l6 e7 f7 g7 h7 j7 l7 d8 e8 f8 g8 h8 j8 l8 e9 f9 g9 h9 j9 l9 f10 l10 g10 nc nc l1 m1 nc nc a2 a1 a0 nc a6 a5 b2 d2 b3 avd# a3 nc a4 v ss dq8 ub# b4 clk a18 a17 dq1 dq2 nc reset# rdy dq11 nc ce2s a20 f5 g5 f6 g6 nc nc nc nc nc a19 b7 nc a9 a10 dq6 dq5 a12 a13 a14 nc dq14 a21 nc b8 b9 d9 nc nc a15 a16 ce#f oe# dq9 dq3 dq4 dq13 dq15 nc nc nc nc v ss v io fnc nc nc ce#1s dq0 dq10 v cc fv cc s dq12 dq7 v ss k2 k3 k4 k5 k6 k7 k8 k9 nc nc m10 nc nc a10 b10 a1 b1 nc nc c3 c4 c5 c6 c7 c8 a7 c2 wp# lb# acc we# a8 a11 nc c9 c1 nc nc nc sram only shared flash only d7 93-ball fbga to p v i e w
november 1, 2002 am42bds640ag 9 preliminary pin description a19?a0 = 20 address inputs (common) a21?a20 = 2 address inputs (flash) dq15?dq0 = 16 data inputs/outputs (common) ce#f = chip enable (flash) ce1#s = chip enable 1 (sram) ce2s = chip enable 2 (sram) oe# = output enable (common) we# = write enable (common) ub#s = upper byte control (sram) lb#s = lower byte control (sram) reset# = hardware reset pin, active low v cc f = flash 1.8 volt-only single power supply (see product selector guide for speed options and voltage sup- ply tolerances) v io f = input & output buffer power supply must be tied to v cc f. v cc s = sram power supply v ss = device ground (common) nc = pin not connected internally rdy = ready output; indicates the status of the burst read. low = data not valid at expected time. high = data valid. clk = clk is not required in asynchronous mode. in burst mode, after the initial word is output, subsequent active edges of clk increment the internal address counter. avd# = address valid input. indicates to de- vice that the valid address is present on the address inputs (a21?a0). low = for asynchronous mode, indi- cates valid address; for burst mode, causes starting address to be latched. high = device ignores address in- puts wp# = hardware write protect input. at v il , disables program and erase func- tions in the two outermost sectors. should be at v ih for all other condi- tions. acc = at v id , accelerates programming; automatically places device in un- lock bypass mode. at v il , locks all sectors. should be at v ih for all other conditions. logic symbol 20 16 dq15?dq0 a19?a0 ce#f oe# we# reset# ub#s rdy wp# a21?a20 lb#s acc ce1#s ce2s avd# clk
10 am42bds640ag november 1, 2002 preliminary ordering information the order number (valid combination) is formed by the following: valid combinations valid combinations list configurat ions planned to be supported in vol- ume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. am42bds640 a g t d 8 i t tape and reel t = 7 inches s = 13 inches temperature range i = industrial (?40 c to +85 c) v io and handshaking features 8 = 1.8 v v io , reduced wait-state handshaking 9 = 1.8 v v io , standard handshaking clock rate/asynchronous speed/sram speed d = 54 mhz/70 ns/70 ns c = 40 mhz/85 ns/85 ns boot sector t = top boot sector b = bottom boot sector process technology g = 0.17 m sram device density a= 16 mbits amd device number/description am42bds640ag stacked multi-chip package (mcp) flash memory and sram am29bds640g 64 megabit (4 m x 16-bit) cmos 1.8 volt-only, simultaneous operation, burst mode flash memory and 16 mbit (1 m x 16-bit) static ram 93-ball fine-pitch ball grid array package, 8.0 x 11.6 mm, 0.8 mm ball pitch (fsc093) valid combinations order number package marking burst frequency (mhz) v io range am42bds640agtd8i am42bds640agbd8i t, s m42000004y m42000004z 54 1.65 ? 1.95 v am42bds640agtd9i am42bds640agbd9i m420000050 m420000051 am42bds640agtc8i am42bds640agbc8i m420000052 m420000053 40 am42bds640agtc9i am42bds640agbc9i m420000054 m420000055
november 1, 2002 am42bds640ag 11 preliminary mcp device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the commands, along with the address and data informa- tion needed to execute the command. the contents of the register serve as inputs to the internal state ma- chine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and control levels they require, and the re- sulting output. the following subsections describe each of these operations in further detail.
12 am42bds640ag november 1, 2002 preliminary table 1. device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 9?11 v, v hh = 9.0 0.5 v, x = don?t care, a in = address in, d in = data in, d out = data out = active edge of clk, = pulse low, = rising edge of pulse low notes: 1. other operations except for those indicated in this column are inhibited. 2. do not apply ce#f = v il , ce1#s = v il and ce2s = v ih at the same time. 3. either ce1#s = v ih or ce2s = v il will disable the sram. if one of these conditions is true, the other ce input is don?t care. 4. x = don?t care or open lb#s or ub#s. 5. default edge of clk is the rising edge. 6. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector lock/unlock command sequence? section. 7. if acc = v hh , all sectors will be protected. 8. if wp# = v il , sectors 0,1 (bottom boot) or sectors 132, 133 (top boot) are protected. if wp# = v ih , the protection applied to the aforementioned sectors depends on whether they were last protected or unprotected using the method described in ?sector lock/unlock command sequence? . note that wp# must not be left floating or unconnected. operation ce#f ce1#s ce2s oe# we# a [21?0] dq [15?8] dq [7?0] lb#s ub#s reset# clk avd# (note 3) (note 4) asynchronous read from flash, addresses latched lh llh a in i/o x x h x asynchronous read from flash, addresses steady state lh llh a in i/o x x h x l asynchronous write to flash l h l h l a in i/o x x h x l synchronous write to flash l h l h l a in i/o x x h x ce# standby h h l x x hi-z hi-z x x h x x output disable l hl h h hi-z hi-z hi-z lx hxx hl xl hardware reset x h l x x hi-z hi-z hi-z x x l x x read from sram h l h l h a in d out d out ll hxx d out hi-z h l hi-z d out lh wirte to sram h l h x l a in d in d in ll hxx d in hi-z h l hi-z d in lh flash burst read operations load starting burst address l h l x h addr in x x x h advance burst to next address with appropriate data presented on the data bus lh llh high z burst data out xx h h terminate current burst read cycle h h l x h hi-z hi-z x x h x terminate current burst read cycle via reset# xh lxhhi-z hi-z xx l xx terminate current burst read cycle and start new burst read cycle l h l x h hi-z i/o x x h
november 1, 2002 am42bds640ag 13 preliminary flash device bus operations requirements for asynchronous read operation (non-burst) to read data from the memory array, the system must first assert a valid address on a21?a0, while driving avd# and ce# to v il . we# should remain at v ih . the rising edge of avd# latches the address. the data will appear on dq15?dq0. since the memory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable addresses and stable ce# to valid data at the outputs. the output enable access time (t oe ) is the delay from the falling edge of oe# to valid data at the output. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. requirements for sy nchronous (burst) read operation the device is capable of continuous sequential burst operation and linear burst operation of a preset length. when the device first powers up, it is enabled for asyn- chronous read operation. prior to entering burst mode, the system should deter- mine how many wait states are desired for the initial word (t iacc ) of each burst access, what mode of burst operation is desired, which edge of the clock will be the active clock edge, and how the rdy signal will transi- tion with valid data. the system would then write the burst mode configuration register command sequence. see ?set burst mode configuration register command sequence? and ?flash command definitions? for further details. once the system has written the ?set burst mode con- figuration register? command sequence, the device is enabled for synchronous reads only. the initial word is output t iacc after the active edge of the first clk cycle. subsequent words are output t bacc after the active edge of each successive clock cycle, which automatically increments the internal address counter. note that the device has a fixed internal address boundary that occurs every 64 words, starting at address 00003fh. during the time the device is out- putting data at this fixed internal address boundary (address 00003fh, 00007fh, 0000bfh, etc.), a two cycle latency occurs before data appears for the next address (address 000040h, 000080h, 0000c0h, etc.). the rdy output indicates this condition to the system by pulsing low. for standard handshaking devices, there is no two cycle latency between 3fh and 40h (or multiple thereof). see table 10 . for reduced wait-state handshaking devices, if the address latched is 3dh (or 64 multiple), an additional cycle latency occurs prior to the initial access. if the address latched is 3eh (or 64 multiple) two additional cycle latency occurs prior to the initial access and the 2 cycle latency between 3fh and 40h (or 64 multiple) will not occur. for 3fh latched addresses (or 64 multiple) three additional cycle latency occurs prior to the initial access and the 2 cycle latency between 3fh and 40h (or 64 multiple) will not occur. the device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location, until the system drives ce# high, reset# low, or avd# low in conjunction with a new address. see table 1, ?device bus operations,? on page 12 . if the host system crosses the bank boundary while reading in burst mode, and the device is not program- ming or erasing, a two-cycle latency will occur as described above in the subsequent bank. if the host system crosses the bank boundary while the device is programming or erasing, th e device will provide read status information. the clock will be ignored. after the host has completed status reads, or the device has completed the program or erase operation, the host can restart a burst operation using a new address and avd# pulse. if the clock frequency is less than 6 mhz during a burst mode operation, additional latencies will occur. rdy indicates the length of the latency by pulsing low. 8-, 16-, and 32-word linear burst with wrap around the remaining three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. in each of these modes, the burst addresses read are determined by the group within which the starting address falls. the groups are sized according to the number of words read in a single burst sequence for a given mode (see table 2 .) table 2. burst address groups as an example: if the starting address in the 8-word mode is 39h, the address range to be read would be 38-3fh, and the burst sequence would be mode group size group address ranges 8-word 8 words 0-7h, 8-fh, 10-17h, ... 16-word 16 words 0-fh, 10-1fh, 20-2fh, ... 32-word 32 words 00-1fh, 20-3fh, 40-5fh, ...
14 am42bds640ag november 1, 2002 preliminary 39-3a-3b-3c-3d-3e-3f-38h-etc. the burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. in a similar fashion, the 16-word and 32-word linear wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. note that in these three burst read modes the address pointer does not cross the boundary that occurs every 64 words; thus, no wait states are inserted (except during the initial access). the rdy pin indicates when data is valid on the bus. the devices can wrap through a maximum of 128 words of data (8 words up to 16 times, 16 words up to 8 times, or 32 words up to 4 times) before requiring a new synchronous access (latching of a new address). burst mode configuration register the device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, rdy configuration, and synchronous mode active. reduced wait-state handshaking option the device can be equipped with a reduced wait-state handshaking feature that allows the host system to simply monitor the rdy signal from the device to deter- mine when the initial word of burst data is ready to be read. the host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. the initial word of burst data is indicated by the rising edge of rdy after oe# goes low. the presence of the reduced wait-state handshaking feature may be verified by writing the autoselect command sequence to the device. see ?autoselect command sequence? for details. for optimal burst mode performance on devices without the reduced wait-state handshaking option, the host system must set the appropriate number of wait states in the flash device depending on clock frequency and the presence of a boundary crossing. see ?set burst mode configuration register command sequence? section on page 23 section for more infor- mation. the device will automatically delay rdy and data by one additional clock cycle when the starting address is odd. the autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. see the ?autoselect command sequence? section for more information. simultaneous read/write operations with zero latency this device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. an erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). figure 33, ?back-to-back read/write cycle timings,? on page 62 shows how read and write cycles may be initiated for simultaneous operation with zero latency. refer to the dc characteristics table for read-while-program and read-while-erase current specifications. writing commands/command sequences the device has the capability of performing an asyn- chronous or synchronous write operation. during a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih . when writing commands or data. during an asynchronous write operation, the system must drive ce# and we# to v il and oe# to v ih when providing an address, command, and data. the asynchronous and synchronous pro- graming operation is independent of the set device read mode bit in the burst mode configuration reg- ister. the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a word, instead of four. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 8, ?programmable wait state settings,? on page 24 indicates the address space that each sector occupies. the device address space is divided into four banks: banks b and c contain only 32 kword sectors, while banks a and d contain both 8 kword boot sectors in addition to 32 kword sec- tors. a ?bank address? is the address bits required to uniquely select a bank. similarly, a ?sector address? is the address bits required to uniquely select a sector. i cc2 in the dc characteristics table represents the active current specification for the write mode. the ac characteristics section cont ains timing specification tables and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the acc function. acc is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v id on this input, the device auto- matically enters the aforementioned unlock bypass
november 1, 2002 am42bds640ag 15 preliminary mode and uses the higher voltage on the input to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v id from the acc input returns the device to normal operation. note that sectors must be unlocked prior to raising acc to v id . note that the acc pin must not be at v id for operations other than accelerated pro- gramming, or device damage may result. in addition, the acc pin must not be left floating or unconnected; inconsistent behavior of the device may result . when at v il , acc locks all sectors. acc should be at v ih for all other conditions. autoselect functions if the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq15?dq0. autoselect mode may only be entered and used when in the asynchronous read mode. refer to the ?autoselect command sequence? section on page 26 section for more information. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the opera- tion is completed. i cc3 in the dc characteristics table represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. while in asynchronous mode, the device automatically enables this mode when addresses remain stable for t acc + 60 ns. the auto- matic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always avail- able to the system. while in synchronous mode, the device automatically enables this mode when either the first active clk edge occurs after t acc or the clk runs slower than 5mhz. note that a new burst opera- tion is required to provide new data. i cc4 in the ?flash dc characteristics? section on page 36 represents the automatic sleep mode current spec- ification. reset#: hardwa re reset input the reset# input provides a hardware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.2 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby current will be greater. reset# may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or erase oper- ation, the device requires a time of t ready (during embedded algorithms) before the device is ready to read data again. if reset# is asserted when a program or erase operation is not executing, the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after reset# returns to v ih . refer to the ac characteristics tables for reset# parameters and to figure 20, ?reset timings,? on page 49 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high imped- ance state. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 14, ?com- mand definitions,? on page 30 for command defini- tions). the device offers two types of data protection at the sector level: the sector lock/unlock command sequence dis- ables or re-enables both program and erase opera- tions in any sector.
16 am42bds640ag november 1, 2002 preliminary when wp# is at v il , sectors 0 and 1 (bottom boot) or sectors 132 and 133 (top boot) are locked. when acc is at v il , all sectors are locked. the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transi- tions, or from system noise. write protect (wp#) the write protect (wp#) input provides a hardware method of protecting data without using v id . if the system asserts v il on the wp# pin, the device disables program and erase functions in sectors 0 and 1 (bottom boot) or sectors 132 and 133 (top boot). if the system asserts v ih on the wp# pin, the device reverts to whether the two outermost 8k byte boot sectors were last set to be protected or unprotected. note that the wp# pin must not be left floating or unconnected; inconsistent behavior of the device may result. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. common flash memo ry interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-indepen- dent, jedec id-independent, and forward- and back- ward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 3-6. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 3-6. the system must write the reset command to return the device to the autoselect mode. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the amd site at the following url: http://www.amd.com/us-en/flashmemory/technical- resources/0,,37_1693_1780_1834^1955,00.html . alternatively, contact an amd representative for copies of these documents. table 3. cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists)
november 1, 2002 am42bds640ag 17 preliminary table 4. system interface string table 5. device geometry definition 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) addresses data description 1bh 0017h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0019h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0004h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0004h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) addresses data description 27h 0017h device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0003h 0000h 0040h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 007dh 0000h 0000h 0001h erase block region 2 information 35h 36h 37h 38h 0003h 0000h 0040h 0000h erase block region 3 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information
18 am42bds640ag november 1, 2002 preliminary table 6. primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0004h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon technology (bits 5-2) 0001 = 0.17 m 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0005h sector protect/unprotect scheme 04 = 29lv800 mode 4ah 0063h simultaneous operation number of sectors in all banks except boot block 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 00xxh top/bottom boot sector flag 02h = bottom boot device, 03h = top boot device 50h 0000h program suspend. 00h = not supported 57h 0004h bank organization: x = number of banks 58h 0023h bank a region information. x = number of sectors in bank 59h 0020h bank b region information. x = number of sectors in bank 5ah 0020h bank c region information. x = number of sectors in bank 5bh 0023h bank d region information. x = number of sectors in bank
november 1, 2002 am42bds640ag 19 preliminary table 7. sector address table sector sector size (x16) address range bank d sa0 8 kwords 000000h-001fffh sa1 8 kwords 002000h-003fffh sa2 8 kwords 004000h-005fffh sa3 8 kwords 006000h-007fffh sa4 32 kwords 008000h-00ffffh sa5 32 kwords 010000h-017fffh sa6 32 kwords 018000h-01ffffh sa7 32 kwords 020000h-027fffh sa8 32 kwords 028000h-02ffffh sa9 32 kwords 030000h-037fffh sa10 32 kwords 038000h-03ffffh sa11 32 kwords 040000h-047fffh sa12 32 kwords 048000h-04ffffh sa13 32 kwords 050000h-057fffh sa14 32 kwords 058000h-05ffffh sa15 32 kwords 060000h-067fffh sa16 32 kwords 068000h-06ffffh sa17 32 kwords 070000h-077fffh sa18 32 kwords 078000h-07ffffh sa19 32 kwords 080000h-087fffh sa20 32 kwords 088000h-08ffffh sa21 32 kwords 090000h-097fffh sa22 32 kwords 098000h-09ffffh sa23 32 kwords 0a0000h-0a7fffh sa24 32 kwords 0a8000h-0affffh sa25 32 kwords 0b0000h-0b7fffh sa26 32 kwords 0b8000h-0bffffh sa27 32 kwords 0c0000h-0c7fffh sa28 32 kwords 0c8000h-0cffffh sa29 32 kwords 0d0000h-0d7fffh sa30 32 kwords 0d8000h-0dffffh sa31 32 kwords 0e0000h-0e7fffh sa32 32 kwords 0e8000h-0effffh sa33 32 kwords 0f0000h-0f7fffh sa34 32 kwords 0f8000h-0fffffh
20 am42bds640ag november 1, 2002 preliminary bank c sa35 32 kwords 100000h-107fffh sa36 32 kwords 108000h-10ffffh sa37 32 kwords 110000h-117fffh sa38 32 kwords 118000h-11ffffh sa39 32 kwords 120000h-127fffh sa40 32 kwords 128000h-12ffffh sa41 32 kwords 130000h-137fffh sa42 32 kwords 138000h-13ffffh sa43 32 kwords 140000h-147fffh sa44 32 kwords 148000h-14ffffh sa45 32 kwords 150000h-157fffh sa46 32 kwords 158000h-15ffffh sa47 32 kwords 160000h-167fffh sa48 32 kwords 168000h-16ffffh sa49 32 kwords 170000h-177fffh sa50 32 kwords 178000h-17ffffh sa51 32 kwords 180000h-187fffh sa52 32 kwords 188000h-18ffffh sa53 32 kwords 190000h-197fffh sa54 32 kwords 198000h-19ffffh sa55 32 kwords 1a0000h-1a7fffh sa56 32 kwords 1a8000h-1affffh sa57 32 kwords 1b0000h-1b7fffh sa58 32 kwords 1b8000h-1bffffh sa59 32 kwords 1c0000h-1c7fffh sa60 32 kwords 1c8000h-1cffffh sa61 32 kwords 1d0000h-1d7fffh sa62 32 kwords 1d8000h-1dffffh sa63 32 kwords 1e0000h-1e7fffh sa64 32 kwords 1e8000h-1effffh sa65 32 kwords 1f0000h-1f7fffh sa66 32 kwords 1f8000h-1fffffh table 7. sector address table (continued) sector sector size (x16) address range
november 1, 2002 am42bds640ag 21 preliminary bank b sa67 32 kwords 200000h-207fffh sa68 32 kwords 208000h-20ffffh sa69 32 kwords 210000h-217fffh sa70 32 kwords 218000h-21ffffh sa71 32 kwords 220000h-227fffh sa72 32 kwords 228000h-22ffffh sa73 32 kwords 230000h-237fffh sa74 32 kwords 238000h-23ffffh sa75 32 kwords 240000h-247fffh sa76 32 kwords 248000h-24ffffh sa77 32 kwords 250000h-257fffh sa78 32 kwords 258000h-25ffffh sa79 32 kwords 260000h-267fffh sa80 32 kwords 268000h-26ffffh sa81 32 kwords 270000h-277fffh sa82 32 kwords 278000h-27ffffh sa83 32 kwords 280000h-287fffh sa84 32 kwords 288000h-28ffffh sa85 32 kwords 290000h-297fffh sa86 32 kwords 298000h-29ffffh sa87 32 kwords 2a0000h-2a7fffh sa88 32 kwords 2a8000h-2affffh sa89 32 kwords 2b0000h-2b7fffh sa90 32 kwords 2b8000h-2bffffh sa91 32 kwords 2c0000h-2c7fffh sa92 32 kwords 2c8000h-2cffffh sa93 32 kwords 2d0000h-2d7fffh sa94 32 kwords 2d8000h-2dffffh sa95 32 kwords 2e0000h-2e7fffh sa96 32 kwords 2e8000h-2effffh sa97 32 kwords 2f0000h-2f7fffh sa98 32 kwords 2f8000h-2fffffh table 7. sector address table (continued) sector sector size (x16) address range
22 am42bds640ag november 1, 2002 preliminary bank a sa99 32k words 300000h-307fffh sa100 32k words 308000h-30ffffh sa101 32k words 310000h-317fffh sa102 32k words 318000h-31ffffh sa103 32k words 320000h-327fffh sa104 32k words 328000h-32ffffh sa105 32k words 330000h-337fffh sa106 32k words 338000h-33ffffh sa107 32k words 340000h-347fffh sa108 32k words 348000h-34ffffh sa109 32k words 350000h-357fffh sa110 32k words 358000h-35ffffh sa111 32k words 360000h-367fffh sa112 32k words 368000h-36ffffh sa113 32k words 370000h-377fffh sa114 32k words 378000h-37ffffh sa115 32k words 380000h-387fffh sa116 32k words 388000h-38ffffh sa117 32k words 390000h-397fffh sa118 32k words 398000h-39ffffh sa119 32k words 3a0000h-3a7fffh sa120 32k words 3a8000h-3affffh sa121 32k words 3b0000h-3b7fffh sa122 32k words 3b8000h-3bffffh sa123 32k words 3c0000h-3c7fffh sa124 32k words 3c8000h-3cffffh sa125 32k words 3d0000h-3d7fffh sa126 32k words 3d8000h-3dffffh sa127 32k words 3e0000h-3e7fffh sa128 32k words 3e8000h-3effffh sa129 32k words 3f0000h-3f7fffh sa130 8k words 3f8000h-3f9fffh sa131 8k words 3fa000h-3fbfffh sa132 8k words 3fc000h-3fdfffh sa133 8k words 3fe000h-3fffffh table 7. sector address table (continued) sector sector size (x16) address range
november 1, 2002 am42bds640ag 23 preliminary flash command definitions writing specific address and data commands or sequences into the command register initiates device operations. table 14, ?command definitions,? on page 30 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. refer to the ac characteristics section for timing dia- grams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data in asynchronous mode. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see the ?erase suspend/erase resume commands? section on page 28 section for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. see the ?reset command? section on page 25 section for more infor- mation. see also ?requirements for asynchronous read oper- ation (non-burst)? and ?requirements for synchronous (burst) read operation? sections for more information. the asynchronous read and synchronous/burst read tables provide the read parameters, and figures 11 , 13 , and 18 show the timings. set burst mode configuration register command sequence the device uses a burst mode configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, rdy con- figuration, and synchronous mode active. the burst mode configuration register must be set before the device will enter burst mode. the burst mode configuration register is loaded with a three-cycle command sequence. the first two cycles are standard unlock sequences. on the third cycle, the data should be c0h, address bits a11?a0 should be 555h, and address bits a19?a12 set the code to be latched. the device will power up or after a hardware reset with the default setting, which is in asynchronous mode. the register must be set before the device can enter synchronous mode. the burst mode configura- tion register can not be changed during device opera- tions (program, erase, or sector lock). figure 1. synchronous/asynchronous state diagram read mode setting on power-up or hardware reset, the device is set to be in asynchronous read mode. this setting allows the system to enable or disable burst mode during system operations. address a19 determines this setting: ?1? for asynchronous mode, ?0? for synchronous mode. programmable wait state configuration the programmable wait state feature informs the device of the number of clock cycles that must elapse after avd# is driven active before data will be available. this value is determined by the input frequency of the device. address bits a14?a12 determine the setting (see table 8 ). the wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. the number of wait states that should be programmed into the device is directly related to the clock frequency. power-up/ hardware reset asynchronous read mode only synchronous read mode only set burst mode configuration register command for synchronous mode (a19 = 0) set burst mode configuration registe r command for asynchronous mode (a19 = 1)
24 am42bds640ag november 1, 2002 preliminary table 8. programmable wait state settings notes: 1. upon power-up or hardware reset, the default setting is seven wait states. 2. rdy will default to being active with data when the wait state setting is set to a total initial access cycle of 2. 3. assumes even address. it is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. a hardware reset will set the wait state to the default set- ting. handshaking option if the device is equipped with reduced wait-state hand- shaking, the host system should set address bits a14?a12 to 010 for a clock frequency of 40 mhz or to 011 for a clock frequency of 54 mhz for the system/device to execute at maximum speed. table 9 describes the typical number of clock cycles (wait states) for various conditions. table 9. initial access codes * in the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (addresses which are multiples of 3fh). the autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. see the ?autoselect command sequence? section for more information. standard handshaking operation for optimal burst mode performance on devices with standard handshaking, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. table 10 describes the typical number of clock cycles (wait states) for various conditions with a14?a12 set to 101. table 10. wait states for standard handshaking * in the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (addresses which are multiples of 3fh). burst read mode configuration the device supports four different burst read modes: continuous mode, and 8, 16, and 32 word linear wrap around modes. a continuous sequence begins at the starting address and advances the address pointer until the burst operation is complete. if the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. for example, an eight-word linear burst with wrap around begins on the starting burst address written to the device and then proceeds until the next 8 word boundary. the address pointer then returns to the first word of the boundary, wrapping back to the starting location. the sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. table 11 shows the address bits and settings for the four burst read modes. a14 a13 a12 total initial access cycles 000 2 001 3 010 4 011 5 100 6 101 7 system frequency range even initial addr. odd initial addr. even initial addr. with boundary* odd initial addr. with boundary* device speed rating 6?11 mhz 2 2 3 4 40 mhz 12?23 mhz 2 3 4 5 24?33 mhz 3 4 5 6 34?40 mhz 4 5 6 7 40?47 mhz 4 5 6 7 54 mhz 48?54 mhz 5 6 7 8 conditions at address typical no. of clock cycles after avd# low 40/54 mhz initial address is even 7 initial address is odd 7 initial address is even, and is at boundary crossing* 7 initial address is odd, and is at boundary crossing* 7
november 1, 2002 am42bds640ag 25 preliminary table 11. burst read mode settings note: upon power-up or hardware reset the default setting is continuous. burst active clock edge configuration by default, the device will deliver data on the rising edge of the clock after the initial synchronous access time. subsequent outputs will also be on the following rising edges, barring any delays. the device can be set so that the falling clock edge is active for all synchro- nous accesses. address bit a17 determines this set- ting; ?1? for rising active, ?0? for falling active. rdy configuration by default, the device is set so that the rdy pin will output v oh whenever there is valid data on the outputs. the device can be set so that rdy goes active one data cycle before active data. address bit a18 deter- mines this setting; ?1? for rdy active with data, ?0? for rdy active one clock cycle before valid data. configuration register table 12 shows the address bits that determine the configuration register settings for various device func- tions. table 12. burst mode configuration register note: device will be in the default state upon power-up or hardware reset. sector lock/unlock command sequence the sector lock/unlock command sequence allows the system to determine which sectors are protected from accidental writes. when the device is first powered up, all sectors are locked. to unlock a sector, the system must write the sector lock/unlock command sequence. two cycles are first written: addresses are don?t care and data is 60h. during the third cycle, the sector address (sla) and unlock command (60h) is written, while specifying with address a6 whether that sector should be locked (a6 = v il ) or unlocked (a6 = v ih ). after the third cycle, the system can continue to lock or unlock additional cycles, or exit the sequence by writing f0h (reset command). note that the last two outermost boot sectors can be locked by taking the wp# signal to v il . reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the bank to which burst modes address bits a16 a15 continuous 0 0 8-word linear wrap around 0 1 16-word linear wrap around 1 0 32-word linear wrap around 1 1 address bit function settings (binary) a19 set device read mode 0 = synchronous read (burst mode) enabled 1 = asynchronous mode (default) a18 rdy 0 = rdy active one clock cycle before data 1 = rdy active with data (default) a17 clock 0 = burst starts and data is output on the falling edge of clk 1 = burst starts and data is output on the rising edge of clk (default) a16 burst read mode 00 = continuous (default) 01 = 8-word linear with wrap around 10 = 16-word linear with wrap around 11 = 32-word linear with wrap around a15 a14 programmable wait state 000 = data is valid on the 2nd active clk edge after avd# transition to v ih 001 = data is valid on the 3rd active clk edge after avd# transition to v ih 010 = data is valid on the 4th active clk edge after avd# transition to v ih 011 = data is valid on the 5th active clk edge after avd# transition to v ih 100 = data is valid on the 6th active clk edge after avd# transition to v ih 101 = data is valid on the 7th active clk edge after avd# transition to v ih (default) a13 a12
26 am42bds640ag november 1, 2002 preliminary the system was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins (prior to the third cycle). this resets the bank to which the system was writing to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend). the reset command is used to exit the sector lock/unlock sequence. autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. table 14, ?command definitions,? on page 30 shows the address and data requirements. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-sus- pend-read mode. the autoselect command may not be written while the device is actively programming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the autoselect command. the bank then enters the autoselect mode. no subsequent data will be made available if the autoselect data is read in synchronous mode. the system may read at any address within the same bank any number of times without initiating another autoselect command sequence. the following table describes the address requirements for the various autoselect functions, and the resulting data. ba represents the bank address, and sa represents the sector address. the device id is read in three cycles. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend). program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 14 shows the address and data requirements for the program command sequence. when the embedded program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by monitoring dq7 or dq6/dq2. refer to the ?flash write operation status? section on page 31 section for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bit to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? table 13. device ids description address read data manufacturer id (ba) + 00h 0001h device id, word 1 (ba) + 01h 227eh device id, word 2, top boot (ba) + 0eh 2204h (1.8 v v io ) device id, word 2, bottom boot (ba) + 0eh 2224h (1.8 v v io ) device id, word 3 (ba) + 0fh 2201h sector block lock/unlock (sa) + 02h 0001 (locked), 0000 (unlocked) handshaking (ba) + 03h 43h (reduced wait-state), 42h (standard)
november 1, 2002 am42bds640ag 27 preliminary unlock bypass command sequence the unlock bypass feature allows the system to prima- rily program to a bank faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. the host system may also initiate the chip erase and sector erase sequences in the unlock bypass mode. the erase command sequences are four cycles in length instead of six cycles. ta b l e 1 4 , ?command definitions,? on page 30 shows the require- ments for the unlock bypass command sequences. during the unlock bypass mode, only the unlock bypass program, unlock bypass sector erase, unlock bypass chip erase, and unlock bypass reset com- mands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the read mode. the device offers accelerated program operations through the acc input. when the system asserts v id on this input, the device automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the acc input to accelerate the operation. figure 2 illustrates the algorithm for the program oper- ation. refer to the erase/program operations table in the ac characteristics section for parameters, and figure 21, ?asynchronous program operation tim- ings,? on page 51 for timing diagrams. figure 2. erase operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 14, ?command definitions,? on page 30 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7 or dq6/dq2. refer to the ?flash write operation status? section on page 31 section for information on these status bits. start write erase command sequence data poll from system data = ffh? no yes erasure completed embedde d erase algorithm in progres s notes: 1. see table 14 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
28 am42bds640ag november 1, 2002 preliminary any commands written during the chip erase operation are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. the command sequence is two cycles cycles in length instead of six cycles. see table 14 for details on the unlock bypass command sequences. figure 2 illustrates the algorithm for the erase opera- tion. refer to the erase/program operations table in the ac characteristics section for parameters and timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 14 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than 35 s occurs. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sec- tors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets that bank to the read mode. the system must rewrite the command sequence and any addi- tional addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out (see ?dq3: sector erase timer? section on page 34 .). the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can determine the status of the erase operation by reading dq7 or dq6/dq2 in the erasing bank. refer to the ?flash write operation status? section on page 31 section for infor- mation on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. the command sequence is four cycles cycles in length instead of six cycles. figure 2 illustrates the algorithm for the erase opera- tion. refer to the erase/program operations table in the ac characteristics section for parameters and timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this command is valid only during the sector erase operation, including the minimum 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 35 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and sus- pends the erase operation. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for information on these status bits.
november 1, 2002 am42bds640ag 29 preliminary after an erase-suspended program operation is com- plete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. refer to the ?flash write operation status? section on page 31 section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the ?autoselect functions? section on page 15 and ?autoselect command sequence? section on page 26 sections for details. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase-suspended bank is required when writing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. figure 3. program operation start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 14 for program command sequence.
30 am42bds640ag november 1, 2002 preliminary command definitions table 14. command definitions legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the rising edge of the avd# pulse. pd = data to be programmed at location pa. data latches on the rising edge of we# pulse. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a21?a14 uniquely select any sector. ba = address of the bank (a21, a20) that is being switched to autoselect mode, is in bypass mode, or is being erased. sla = address of the sector to be locked. set sector address (sa) and either a6 = 1 for unlocked or a6 = 0 for locked. cr = configuration register address bits a19?a12. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a21?a12 are don?t cares. 6. no unlock or command cycles required when bank is reading array data. 7. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information) or performing sector lock/unlock. 8. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address. see the autoselect command sequence section for more information. 9. the data in the fifth cycle is 2204h for top boot, 2224h for bottom boot. 10. the data is 0000h for an unlocked sector and 0001h for a locked sector 11. the data is 0043h for reduced wait-state handshaking and 0042h standard handshaking. 12. the unlock bypass command sequence is required prior to this command sequence. 13. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode. 14. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 15. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 16. see ?set burst mode configuration register command sequence? for details. 17. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (notes) cycles bus cycles (notes 1?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data asynchronous read (6) 1 ra rd reset (7) 1 xxx f0 autoselect (8) manufacturer id 4 555 aa 2aa 55 (ba)555 90 (ba)x00 0001 device id (9) 6 555 aa 2aa 55 (ba)555 90 (ba)x01 227e (ba) x0e (note 9) (ba) x0f 2201 sector lock verify (10) 4 555 aa 2aa 55 (sa)555 90 (sa)x02 0000/0001 handshaking option (11) 4 555 aa 2aa 55 (ba)555 90 (ba)x03 0042/0043 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (12) 2 xxx a0 pa pd unlock bypass sector erase (12) 2 xxx 80 sa 30 unlock bypass chip erase (12) 2 xxx 80 xxx 10 unlock bypass reset (13) 2 ba 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (14) 1 ba b0 erase resume (15) 1 ba 30 sector lock/unlock 3 xxx 60 xxx 60 sla 60 set burst mode configuration register (16) 3 555 aa 2aa 55 (cr)555 c0 cfi query (17) 1 55 98
november 1, 2002 am42bds640ag 31 preliminary flash write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 16, ?write operation status,? on page 34 and the following subsections describe the function of these bits. dq7 and dq6 each offers a method for determining whether a program or erase operation is complete or in progress. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algo- rithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to pro- gramming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq6?dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq6?dq0 may be still invalid. valid data on dq7?dq0 will appear on succes- sive read cycles. table 16 shows the outputs for data# polling on dq7. figure 3 shows the data# polling algorithm. figure 27, ?data# polling timings (during embedded algorithm),? on page 57 in the ac characteristics section shows the data# polling timing diagram. notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. figure 4. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
32 am42bds640ag november 1, 2002 preliminary rdy: ready the rdy is a dedicated output that, by default, indi- cates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. using the rdy configuration command sequence, rdy can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. rdy functions only while reading data in burst mode. the following conditions cause the rdy output to be low: during the initial access (in burst mode), and after the boundary that occurs every 64 words beginning with the 64th address, 3fh. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause dq6 to toggle. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are pro- tected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 ms after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. see the following for additional information: figure 4 (toggle bit flowchart), dq6: toggle bit i (description), figure 28, ?toggle bit timings (during embedded algorithm),? on page 57 (toggle bit timing diagram), and table 15, ?dq6 and dq2 indica- tions,? on page 33 . figure 5. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit start no yes yes dq5 = 1? no yes dq6 = toggle? no read byte (dq7?dq0) address = va dq6 = toggle? read byte twice (dq7?dq0) adrdess = va read byte (dq7?dq0) address = va fail pass n ote: the system should recheck the toggle bit even if dq 5 = ?1? because the toggle bit may stop toggling as dq5 c hanges to ?1.? see the subsections on dq6 and dq2 for m ore information.
november 1, 2002 am42bds640ag 33 preliminary ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by com- parison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode informa- tion. refer to table 15 to compare outputs for dq2 and dq6. see the following for additional information: figure 5, ?toggle bit algorithm,? on page 32, see ?dq6: toggle bit i? on page 32., figure 28, ?toggle bit timings (during embedded algorithm),? on page 57 , and table 15, ?dq6 and dq2 indications,? on page 33 . table 15. dq6 and dq2 indications reading toggle bits dq6/dq2 refer to figure 4 for the following discussion. when- ever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has com- pleted the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog- gling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 4). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully com- pleted. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). if device is and the system reads then dq6 and dq2 programming, at any address, toggles, does not toggle. actively erasing, at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. erase suspended, at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. the system can read from any sector not selected for erasure. programming in erase suspend at any address, toggles, is not applicable.
34 am42bds640ag november 1, 2002 preliminary dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence sec- tion. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 16 shows the status of dq3 relative to the other status bits. table 16. write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank. 4. the system may read either asynchronously or synchronously (burst) while in erase suspend. rdy will function exactly as in non-erase-suspended mode. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle embedded erase algorithm 0 toggle 0 1 toggle erase suspend mode erase-suspend- read (note 4) erase suspended sector 1 no toggle 0 n/a toggle non-erase suspended sector data data data data data erase-suspend-program dq7# toggle 0 n/a n/a
november 1, 2002 am42bds640ag 35 preliminary absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . ?65c to +125c voltage with respect to ground: all inputs and i/os except as noted below (note 1) . . . . . . . ?0.5 v to v io + 0.5 v v cc f/v cc s (note 1) . . . . . . . . . . . . .?0.5 v to +2.5 v v io . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +1.95 v acc . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +12.5 v output short circuit current (note 3) . . . . . . 100 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns during voltage transitions inputs might overshoot to v cc +0.5 v for periods up to 20 ns. see figure 6. maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 7. 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 3. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the de- vice at these or any other conditions above those indi- cated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rat- ing conditions for extended periods may affect device reli- ability. figure 6. maximum negative overshoot waveform figure 7. maximum positive overshoot waveform operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . . . . 0c to +70c industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c supply voltages v cc supply voltages . . . . . . . . . . .+1.65 v to +1.95 v v io supply voltages: v io v cc . . . . . . . . . . . . . . . . . . . +1.65 v to +1.95 v operating ranges define those limits between which the func- tionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 1.0 v
36 am42bds640ag november 1, 2002 preliminary flash dc characteristics cmos compatible note: 1. maximum i cc specifications are tested with v cc = v cc max. 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. i cc active while embedded erase or embedded program is in progress. 4. device enters automatic sleep mode when addresses are stable for t acc + 60 ns. typical sleep mode current is equal to i cc3 . 5. total current during accelerated programming is the sum of v acc and v cc currents. parameter description test conditions (note 1) min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current ce# = v il , oe# = v il , we# = v ih 10 20 ma i io1 v io active read current v io = 1.8 v, ce# = v il , oe# = v il , we# = v ih 15 30 ma i io2 v io non-active output v io = 1.8 v, oe# = v ih 0.2 10 a i cc1 v cc active asynchronous read current (note 2) ce# = v il , oe# = v ih , we# = v ih 5 mhz 12 16 ma 1 mhz 3.5 5 ma i cc2 v cc active write current (note 3) ce# = v il , oe# = v ih , v pp = v ih 15 40 ma i cc3 v cc standby current (note 4) ce# = reset# = v cc 0.2 v 0.2 10 a i cc4 v cc reset current reset# = v il, clk = v il 0.2 10 a i cc5 v cc active current (read while write) ce# = v il , oe# = v ih 25 60 ma i acc accelerated program current (note 5) ce# = v il , oe# = v ih, v acc = 12.0 0.5 v v acc 715ma v cc 510ma v il input low voltage v io = 1.8 v ?0.5 0.2 v v ih input high voltage v io = 1.8 v v io ? 0.2 v io + 0.2 v v ol output low voltage i ol = 100 a, v cc = v cc min , v io = v io min 0.1 v v oh output high voltage i oh = ?100 a, v cc = v cc min , v io = v io min v io ? 0.1 v v id voltage for accelerated program 11.5 12.5 v v lko low v cc lock-out voltage 1.0 1.4 v
november 1, 2002 am42bds640ag 37 preliminary notes: 1. typical values measured at v cc = 2.0 v, t a = 25 c. not 100% tested. 2. undershoot is ?1.0 v when pulse width 20 ns. 3. overshoot is v cc + 1.0 v when pulse width 20 ns. 4. overshoot and undershoot are sampled, not 100% tested. sram dc and operating characteristics parameter symbol parameter description test conditions min typ max unit i li input leakage current v in = v ss to v cc ?1.0 1.0 a i lo output leakage current ce1#s = v ih , ce2s = v il or oe# = v ih or we# = v il , v io = v ss to v cc ?1.0 1.0 a i cc operating power supply current i io = 0 ma, ce1#s = v il , ce2s = we# = v ih , v in = v ih or v il 5ma i cc1 s average operating current cycle time = 1 s, 100% duty, i io = 0 ma, ce1#s 0.2 v, ce2 v cc ? 0.2 v, v in 0.2 v or v in v cc ? 0.2 v 13ma i cc2 s average operating current cycle time = min., i io = 0 ma, 100% duty, ce1#s = v il , ce2s = v ih , v in = v il = or v ih 825ma v ol output low voltage i ol = 0.1 ma 0.2 v v oh output high voltage i oh = ?0.1 ma 1.4 v i sb1 standby current (cmos) ce1#s v cc ? 0.2 v, ce2 v cc ? 0.2 v (ce1#s controlled) or ce2 0.2 v (ce2s controlled), cios = v ss or v cc , other input = 0 ~ v cc 15 a v il input low voltage ?0.2 (note 2) 0.4 v v ih input high voltage 1.4 v cc +0.2 (note 3) v
38 am42bds640ag november 1, 2002 preliminary test conditions table 17. test specifications key to switching waveforms c l device under te s t figure 8. test setup test condition all speed options unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?v io v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input figure 9. input waveforms and measurement levels
november 1, 2002 am42bds640ag 39 preliminary ac characteristics sram ce#s timing figure 10. timing diagram for alternating between sram and flash parameter description test setup all speeds unit jedec std ?t ccr ce#s recover time ? min 0 ns c e#f t ccr t ccr c e1#s c e2s t ccr t ccr
40 am42bds640ag november 1, 2002 preliminary flash ac characteristics synchronous/burst read note: 1. addresses are latched on the first of either the active edge of clk or the rising edge of avd#. parameter description d8 (54 mhz) c8 (40 mhz) unit jedec standard t iacc latency (even address in reduced wait-state handshaking mode) max 87.5 95 ns parameter description d8, d9 (54 mhz) c8, c9 (40 mhz) unit jedec standard t iacc latency?(odd address in handshaking mode or standard handshaking) max 106 120 ns t bacc burst access time valid clock to output delay max 13.5 20 ns t acs address setup time to clk (note 1) min 5 ns t ach address hold time from clk (note 1) min 7 ns t bdh data hold time from next clock cycle max 4 ns t oe output enable to output valid max 13.5 20 ns t cez chip enable to high z max 10 ns t oez output enable to high z max 10 ns t ces ce# setup time to clk min 5 ns t rdys rdy setup time to clk min 5 ns t racc ready access time from clk max 13.5 20 ns t aas address setup time to avd# (note 1) min 5 ns t aah address hold time to avd# (note 1) min 7 ns t cas ce# setup time to avd# min 0 ns t avc avd# low to clk min 5 ns t avd avd# pulse min 12 ns t acc access time max 70 ns
november 1, 2002 am42bds640ag 41 preliminary ac characteristics notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. 2. if any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by rdy. 3. the device is in synchronous mode. figure 11. clk synchronous burst mode read (rising active clk) da da + 1 da + n oe# dq15 - dq0 a21 - a0 aa avd# rdy clk ce#f t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t acc t bdh 7 cycles for initial access shown. hi-z hi-z hi-z 1 2 34 56 7 t rdys t bacc
42 am42bds640ag november 1, 2002 preliminary ac characteristics notes: 1. figure shows total number of wait states set to four cycles. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active falling edge. 2. if any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by rdy. 3. the device is in synchronous mode. 4. a17 = 0. figure 12. clk synchronous burst mode read (falling active clock) da da + 1 da + n oe# dq15 - dq0 a21 - a0 aa avd# rdy clk ce#f t ces t acs t avc t avd t ach t oe t oez t cez t iacc t acc t bdh 4 cycles for initial access shown. t racc hi-z hi-z hi-z 12345 t rdys t bacc
november 1, 2002 am42bds640ag 43 preliminary ac characteristics notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active rising edge. 2. if any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by rdy. 3. the device is in synchronous mode. 4. a17 = 1. figure 13. synchronous burst mode read note: figure assumes 7 wait states for initial access, 54 mhz clock, and automatic detect synchronous read. d0?d7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. data will wrap around within the 8 words non-stop unless the reset# is asserted low, or avd# latches in another address. starting address in figure is the 7th address in range (a6). see ?requirements for synchronou s (burst) read operation?. the set configuration register command sequence has been written with a18=1; device will output rdy with valid data. figure 14. 8-word linear burst with wrap around da da + 1 da + n oe# dq15 - dq0 a21 - a0 aa avd# rdy clk ce# t cas t aas t avc t avd t aah t oe t racc t oez t cez t iacc t bdh 7 cycles for initial access shown. hi-z hi-z hi-z 1234567 t rdys t bacc t acc f d6 d7 oe# dq15 - dq0 a21 - a0 aa avd# rdy clk ce#f t ces t acs t avds t avd t ach t oe t iacc t bdh d0 d1 d5 d6 7 cycles for initial access shown. 18.5 ns typ. (54 mhz) hi-z t racc 1 234567 t rdys t bacc t acc
44 am42bds640ag november 1, 2002 preliminary ac characteristics note: figure assumes 6 wait states for initial access, 40 mhz clock, and synchronous read. the set configuration register command sequence has been written with a18=0; device will output rdy one cycle before valid data. figure 15. burst with rdy set one cycle before data d1 d0 d2 d3 da + n oe# dq15 - dq0 a21 - a0 aa avd# rdy clk ce#f t ces t acs t avds t avd t ach t oe t racc t oez t cez t iacc t bdh 6 wait cycles for initial access shown. 25 ns typ. (40 mhz) hi-z hi-z hi-z 1 23456 t rdys t bacc t acc
november 1, 2002 am42bds640ag 45 preliminary ac characteristics notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active rising edge. 2. if any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by rdy. 3. the device is in synchronous mode. 4. this waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under a clk synchronous burst mode. figure 16. reduced wait-state handshaking burst mode read starting at an even address da da + 1 da + n oe# dq15 - dq0 a21 - a0 aa avd# rdy clk ce#f t cas t aas t avc t avd t aah t oe t racc t oez t cez t iacc t bdh 7 cycles for initial access shown. hi-z hi-z hi-z 1234567 t rdys t bacc t acc
46 am42bds640ag november 1, 2002 preliminary ac characteristics figure 17. reduced wait-state handshaking burst mode read starting at an odd address notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active rising edge. 2. if any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by rdy. 3. the device is in synchronous mode. 4. this waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under a clk synchronous burst mode. da da + 1 da + n oe# dq15 - dq0 a21 - a0 aa avd# rdy clk ce#f t cas t aas t avc t avd t aah t oe t racc t oez t cez t iacc t bdh 7 cycles for initial access shown. hi-z hi-z hi-z 12345 78 t rdys t bacc t acc 6
november 1, 2002 am42bds640ag 47 preliminary ac characteristics asynchronous read notes: 1. asynchronous access time is from the last of either stable addresses or the falling edge of avd#. 2. not 100% tested. note: ra = read address, rd = read data. figure 18. asynchronous mode read with latched addresses parameter description d8, d9 (54 mhz) c8, c9 (40 mhz) unit jedec standard t ce access time from ce# low max 70 85 ns t acc asynchronous access time (note 1) max 70 85 ns t avdp avd# low time min 12 ns t aavds address setup time to rising edge of avd min 5 ns t aavdh address hold time from rising edge of avd min 7 ns t oe output enable to output valid max 13.5 20 ns t oeh output enable hold time read min 0 ns toggle and data# polling min 10 ns t oez output enable to high z (note 2) max 10 10.5 ns t cas ce# setup time to avd# min 0 ns t ce we# a21 - a0 ce#f oe# valid rd t acc t oeh t oe d q15 - dq0 t oez t aavdh t avdp t aavds avd# ra t cas
48 am42bds640ag november 1, 2002 preliminary ac characteristics note: ra = read address, rd = read data. figure 19. asynchronous mode read t ce we# a21 - a0 ce#f oe# valid rd t acc t oeh t oe dq15 - dq0 t oez avd# ra
november 1, 2002 am42bds640ag 49 preliminary ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t readyw reset# pin low (during embedded algorithms) to read mode (see note) max 35 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 200 ns t rpd reset# low to standby mode min 20 s reset# t rp t readyw reset timings not during embedded algorithms t ready ce#f, oe# t rh ce#f, oe# reset timings during embedded algorithms reset# t rp figure 20. reset timings
50 am42bds640ag november 1, 2002 preliminary ac characteristics erase/program operations notes: 1. not 100% tested. 2. in asynchronous timing, addresses are latched on the falling edge of we#. in synchronous mode, addresses are latched on the first of either the rising edge of avd# or the active edge of clk. 3. see the ?flash erase and programming performance? section for more information. 4. does not include the preprogramming time. parameter description all speed options unit jedec standard t avav t wc write cycle time (note 1) min 80 ns t avwl t as address setup time (note 2) synchronous min 5 ns asynchronous 0 t wlax t ah address hold time (note 2) synchronous min 7 ns asynchronous 45 t acs address setup time to clk (note 2) min 5 ns t ach address hold time to clk (note 2) min 7 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write min 0 ns t cas ce# setup time to avd# min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 50 ns t whwl t wph write pulse width high min 30 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 3) typ 8 s t whwh1 t whwh1 accelerated programming operation (note 3) typ 2.5 s t whwh2 t whwh2 sector erase operation (notes 3, 4) typ 0.2 sec chip erase operation (notes 3, 4) 26.8 t vid v acc rise and fall time min 500 ns t vids v acc setup time (during accelerated programming) min 1 s t vcs v cc setup time min 50 s t csw1 clock setup time to we# (asynchronous) min 5 ns t csw2 clock setup time to we# (synchronous) min 1 ns t chw clock hold time from we# min 1 ns t elwl t cs ce# setup time to we# min 0 ns t avsw avd# setup time to we# min 5 ns t avhw avd# hold time to we# min 5 ns t avhc avd# hold time to clk min 5 ns t avdp avd# low time min 12 ns
november 1, 2002 am42bds640ag 51 preliminary ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a21?a12 are don?t care during command sequence unlock cycles. 4. clk can be either v il or v ih . 5. the asynchronous programming operation is independent of the set device read mode bit in the burst mode configuration register. 6. avd# must toggle during command sequence if clk is at v ih . figure 21. asynchronous program operation timings oe# ce#f data addresses avd# we# clk v cc 555h pd t as t avsw t avhw t csw1 t ah t wc t wph pa t vcs t wp t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h t cs (note 4) (note 6)
52 am42bds640ag november 1, 2002 preliminary ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a21?a12 are don?t care during command sequence unlock cycles. 4. clk can be either v il or v ih . 5. the asynchronous programming operation is independent of the set device read mode bit in the burst mode configuration register. 6. avd# must toggle during command sequence if clk is at v ih . figure 22. alternate asynchronous program operation timings oe# ce#f data addresses avd# we# clk v cc 555h pd t as t avsw t avhw t chw t ah t wc t wph pa t vcs t wp t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h t cs (note 4)
november 1, 2002 am42bds640ag 53 preliminary ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a21?a12 are don?t care during command sequence unlock cycles. 4. addresses are latched on the first of either the rising edge of avd# or the active edge of clk. 5. either cs# or avd# is required to go from low to high in between programming command sequences. 6. the synchronous programming operation is independent of the set device read mode bit in the burst mode configuration register. 7. clk must not have an active edge while we# is at v il . 8. avd# must toggle during command sequence unlock cy- cles. figure 23. synchronous program operation timings oe# ce#f data addresses avd# we# clk v cc 555h pd t as t wp t ah t wc t wph pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t ahw t acs t cas t ach
54 am42bds640ag november 1, 2002 preliminary ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a21?a12 are don?t care during command sequence unlock cycles. 4. addresses are latched on the first of either the rising edge of avd# or the active edge of clk. 5. either cs# or avd# is required to go from low to high in between programming command sequences. 6. the synchronous programming operation is independent of the set device read mode bit in the burst mode configuration register. 7. avd# must toggle during command sequence unlock cy- cles. 8. t ah = 45 ns. 9. clk must not have an active edge while we# is at v il . figure 24. alternate synchronous program operation timings oe# ce#f data addresses avd# we# clk v cc 555h pd t ah t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t acs t cas t ach t avch t csw2 t as (note 8)
november 1, 2002 am42bds640ag 55 preliminary ac characteristics figure 25. chip/sector erase command sequence notes: 1. sa is the sector address for sector erase. 2. address bits a21?a12 are don?t cares during unlock cycles in the command sequence. oe# ce#f data addresses avd# we# clk v cc t as t wp t ah t wc t wph sa t vcs t cs t dh t ch in progress t whwh2 va complete va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp 55h 2aah 30h
56 am42bds640ag november 1, 2002 preliminary ac characteristics note: use setup and hold times from conventional program operation. figure 26. accelerated unlock bypass programming timing ce#f avd# we# addresses data oe# acc don't care don't care a0h don't care pa pd v id 1 s v il or v ih t vid t vids
november 1, 2002 am42bds640ag 57 preliminary ac characteristics notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, and data# polling will output true data. 3. avd# must toggle between data reads. figure 27. data# polling timings (during embedded algorithm) notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. 3. avd# must toggle between data reads. figure 28. toggle bit timings (during embedded algorithm) we# ce#f oe# t oe addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data we# ce#f oe# t oe addresses data avd# t oeh t ce t ch t oez t cez status data status data t acc va va
58 am42bds640ag november 1, 2002 preliminary ac characteristics notes: 1. the timings are similar to synchronous read timings. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. 3. rdy is active with data (a18 = 0 in the burst mode configuration register). when a18 = 1 in the burst mode configuration register, rdy is active one clock cycle before data. 4. avd# must toggle between data reads. figure 29. synchronous data polling timings/toggle bit timings c e#f c lk a vd# a ddresses o e# d ata r dy status data status data va va t iacc t iacc
november 1, 2002 am42bds640ag 59 preliminary ac characteristics) notes: 1. rdy active with data (a18 = 0 in the burst mode configuration register). 2. rdy active one clock cycle before data (a18 = 1 in the burst mode configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. figure shows the device not crossing a bank in the process of performing an erase or program. figure 30. latency with boundary crossing clk address (hex) c60 c61 c62 c63 c63 c63 c64 c65 c66 c67 d60 d61 d62 d63 d64 d65 d66 d67 (stays high) avd# rdy data address boundary occurs every 64 words, beginning at address 00003fh (00007fh, 0000bfh, etc.). address 000000h is also a boundary crossing. 3c 3d 3e 3f 3f 3f 40 41 42 43 latency rdy latency t racc (note 1) (note 2) t racc t racc t racc
60 am42bds640ag november 1, 2002 preliminary ac characteristics notes: 1. rdy active with data (a18 = 0 in the burst mode configuration register). 2. rdy active one clock cycle before data (a18 = 1 in the burst mode configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. figure shows the device crossing a bank in the process of performing an erase or program. figure 31. latency with boundary crossing into program/erase bank clk address (hex) c60 c61 c62 c63 c63 c63 c64 d60 d61 d62 d63 read status (stays high) avd# rdy data oe#, ce#f (stays low) address boundary occurs every 64 words, beginning at address 00003fh (00007fh, 0000bfh, etc.). address 000000h is also a boundary crossing 3c 3d 3e 3f 3f 3f 40 latency rdy latency t racc (note 1) (note 2) t racc t racc t racc invalid
november 1, 2002 am42bds640ag 61 preliminary ac characteristics wait state decoding addresses: a14, a13, a12 = ?101? ? 5 programmed, 7 total a14, a13, a12 = ?100? ? 4 programmed, 6 total a14, a13, a12 = ?011? ? 3 programmed, 5 total a14, a13, a12 = ?010? ? 2 programmed, 4 total a14, a13, a12 = ?001? ? 1 programmed, 3 total a14, a13, a12 = ?000? ? 0 programmed, 2 total note: figure assumes address d0 is not at an address boundary, active clock edge is rising, and wait state is set to ?101?. figure 32. example of wait states insertion (standard handshaking device) data a vd# oe# clk 12345 d0 d 1 01 6 2 7 3 total number of clock cycles following avd# falling edge rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles programmed 45
62 am42bds640ag november 1, 2002 preliminary ac characteristics note: breakpoints in waveforms indicate that system may alternately read array data from the ?non-busy bank? while checking the status of the program or erase operation in the ?busy? bank. the system should read status twice to ensure valid informatio n. figure 33. back-to-back read/write cycle timings oe# ce#f we# t oeh data a ddresses avd# pd/30h aah ra pa/sa t wc t ds t dh t rc t rc t oe t as t ah t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph
november 1, 2002 am42bds640ag 63 preliminary sram ac characteristics read cycle note: ce1#s = oe# = v il , ce2s = we# = v ih , ub#s and/or lb#s = v il figure 34. sram read cycle?address controlled parameter symbol description d8, d9 (54 mhz) c8, c9 (40 mhz) unit t rc read cycle time min 70 85 ns t aa address access time max 70 85 ns t co1 , t co2 chip enable to output max 70 85 ns t oe output enable access time max 35 40 ns t ba lb#s, ub#s to access time max 70 85 ns t lz1 , t lz2 chip enable (ce1#s low and ce2s high) to low-z output min 10 ns t blz ub#, lb# enable to low-z output min 10 ns t olz output enable to low-z output min 5 ns t hz1 , t hz2 chip disable to high-z output max 25 ns t bhz ub#s, lb#s disable to high-z output max 25 ns t ohz output disable to high-z output max 25 ns t oh output data hold from address change min 10 ns a ddress d ata out previous data valid data valid t aa t rc t oh
64 am42bds640ag november 1, 2002 preliminary sram ac characteristics figure 35. sram read cycle notes: 1. we# = v ih . 2. t hz and t ohz are defined as the time at which the outputs achieve th e open circuit conditions and are not referenced to output voltage levels. 3. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given dev ice and from device to device interconnection. data valid high-z t rc c s#1 a ddress u b#, lb# o e# d ata out t oh t aa t co1 t ba t oe t olz t blz t lz t ohz t bhz t hz c s2 t co2
november 1, 2002 am42bds640ag 65 preliminary sram ac characteristics write cycle notes: 1. we# controlled. 2. t cw is measured from ce1#s going low to the end of write. 3. t wr is measured from the end of write to the address change. t wr applied in case a write ends as ce1#s or we# going high. 4. t as is measured from the address valid to the beginning of write. 5. a write occurs during the overlap (t wp ) of low ce#1 and low we#. a write begins when ce1#s goes low and we# goes low when asserting ub#s or lb#s for a single byte operation or simult aneously asserting ub#s and lb#s for a double byte operation. a write ends at the earliest transition when ce1#s goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. figure 36. sram write cycle?we# control parameter symbol description d8, d9 (54 mhz) c8, c9 (40 mhz) unit t wc write cycle time min 70 85 ns t cw chip enable to end of write min 60 70 ns t as address setup time min 0 ns t aw address valid to end of write min 60 70 ns t bw ub#s, lb#s to end of write min 60 70 ns t wp write pulse time min 50 60 ns t wr write recovery time min 0 ns t whz write to output high-z min 0 ns max 20 t dw data to write time overlap min 30 ns t dh data hold from write time min 0 ns t ow end write to output low-z min 5 ns a ddress c s1#s u b#s, lb#s w e# d ata in d ata out t wc t cw (see note 2) t aw high-z high-z data valid c s2s t cw (see note 2) t bw t wp (see note 5) t as (see note 4) t wr (see note 3) t whz t dw t dh t ow (see note 9) (see note 9) (see note 7) (see note 6)
66 am42bds640ag november 1, 2002 preliminary sram ac characteristics notes: 1. ce1#s controlled. 2. t cw is measured from ce1#s going low to the end of write. 3. t wr is measured from the end of write to the address change. t wr applied in case a write ends as ce1#s or we# going high. 4. t as is measured from the address valid to the beginning of write. 5. a write occurs during the overlap (t wp ) of low ce#1 and low we#. a write begins when ce1#s goes low and we# goes low when asserting ub#s or lb#s for a single byte operation or simult aneously asserting ub#s and lb#s for a double byte operation. a write ends at the earliest transition when ce1#s goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. figure 37. sram write cycle?ce1#s control a ddress data valid u b#s, lb#s w e# d ata in d ata out high-z high-z t wc c e1#s c e2s t aw t as (see note 2) t bw t cw (see note 3) t wr (see note 4) t wp (see note 5) t dw t dh (see note 6)
november 1, 2002 am42bds640ag 67 preliminary sram ac characteristics notes: 1. ub#s and lb#s controlled. 2. t cw is measured from ce1#s going low to the end of write. 3. t wr is measured from the end of write to the address change. t wr applied in case a write ends as ce1#s or we# going high. 4. t as is measured from the address valid to the beginning of write. 5. a write occurs during the overlap (t wp ) of low ce#1 and low we#. a write begins when ce1#s goes low and we# goes low when asserting ub#s or lb#s for a single byte operation or simult aneously asserting ub#s and lb#s for a double byte operation. a write ends at the earliest transition when ce1#s goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. figure 38. sram write cycle?ub#s and lb#s control a ddress data valid u b#s, lb#s w e# d ata in d ata out high-z high-z t wc c e1#s c e2s t aw t bw t dw t dh t wr (see note 3) t as (see note 4) t cw (see note 2) t cw (see note 2) t wp (see note 5)
68 am42bds640ag november 1, 2002 preliminary flash erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 2.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90 c, v cc = 1.8 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute t he two- or four-bus-cycle sequence for the program command. see table 14 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 1,000,000 cycles. flash latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. package pin capacitance note: test conditions t a = 25c, f = 1.0 mhz. flash data retention parameter typ (note 1) max (note 2) unit comments sector erase time (32 kword or 8 kword) 0.4 5 sec excludes 00h programming prior to erasure (note 4) chip erase time 54 sec word program time 11.5 210 s excludes system level overhead (note 5) accelerated word program time 4 120 s chip program time (note 3) 48 144 sec accelerated chip program time 16 48 sec description min max input voltage with respect to v ss on all pins except i/o pins (including oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter symbol description test setup typ max unit c in input capacitance v in = 0 11 14 pf c out output capacitance v out = 0 12 16 pf c in2 control pin capacitance v in = 0 14 16 pf c in3 wp#/acc pin capacitance v in = 0 17 20 pf parameter description test conditions min unit minimum pattern data retention time 150 c10years 125 c20years
november 1, 2002 am42bds640ag 69 preliminary sram data retention notes: 1. ce1#s v cc ? 0.2 v, ce2s v cc ? 0.2 v (ce1#s controlled) or ce2s 0.2 v (ce2s controlled). 2. typical values are not 100% tested. figure 39. ce1#s controlled data retention mode figure 40. ce2s controlled data retention mode parameter symbol parameter description test setup min typ max unit v dr v cc for data retention cs1#s v cc ? 0.2 v (note 1) 1.0 2.2 v i dr data retention current v cc = 1.2 v, ce1#s v cc ? 0.2 v (note 1) 1.0 (note 2) 8a t sdr data retention set-up time see data retention waveforms 0ns t rdr recovery time t rc ns v dr v cc 2 .7v 2 .2v c e1#s g nd data retention mode ce1#s v cc - 0.2 v t sdr t rdr v cc 2 .7 v 0 .4 v v dr c e2s g nd data retention mode t sdr t rdr ce2s < 0.2 v
70 am42bds640ag november 1, 2002 preliminary physical dimensions fsc093?93-ball fine-pitch grid array 8 x 11.6 mm 3187\38.14a n/a 8.00 mm x 11.60 mm package fsc 093 nom. --- --- --- 1.40 --- 1.10 max. 8.00 bsc. 11.60 bsc. 12 --- min. 1.00 0.25 8.80 bsc. 7.20 bsc. 10 93 0.35 0.40 0.40 bsc a2,a3,a4,a5,a6,a7,a8,a9 c10,d1,d10,e1,e10,h1,h10 j1,j10,k1,k10 m2,m3,m4,m5,m6,m7,m8,m9 0.30 0.80 bsc me d jedec package symbol a a2 a1 md d1 e e1 n note depopulated solder ball matrix size e direction matrix footprint ball pitch 0.80 bsc ball pitch solder ball placement body size ball height body size body thickness profile ball diameter matrix size d direction ball count matrix footprint ee ed sd/se notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indention or other means. b o 93x 6 b 0.20 c c c side view a2 a1 a 0.08 0.15 m c mc ab 0.08 10 index mark c 0.15 (2x) (2x) c 0.15 b a d e pin a1 top view corner l m ed corner e1 7 se d1 a b dc e f hg 10 8 9 7 5 6 4 2 3 j k 1 ee sd bottom view pin a1 7
november 1, 2002 am42bds640ag 71 preliminary revision summary revision a (may 20, 2002) initial release. revision b (november 1, 2002) global renamed non-handshaking to standard handshaking. renamed handshaking enabled to reduced wait-state handshaking. product selector guide revised with renamed speed options and added syn- chronous access time with reduced wait-state handshaking. added asynchronous access time ordering information revised with global changes revised valid combinations with updated ordering information. trademarks copyright ? 2002 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are regi stered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication ar e for identification purposes only and may be trademarks of their respective companies .

▲Up To Search▲

Price & Availability of AM42BDS640AGBD8IT

	To Download AM42BDS640AGBD8IT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .